A High-Speed, Light Weight Hardware Architecture for H.264- Compatible Compression on an FPGA
| dc.contributor.advisor | Hanna, Darrin M | |
| dc.contributor.author | Tayyebi, Azam | |
| dc.contributor.other | Louie, Geoffrey | |
| dc.contributor.other | Alawneh, Shadi G | |
| dc.contributor.other | Cesmelioglu, Aycil | |
| dc.date.accessioned | 2024-10-02T13:31:39Z | |
| dc.date.available | 2024-10-02T13:31:39Z | |
| dc.date.issued | 2023-01-01 | |
| dc.description.abstract | Video compression is a technique that reduces and removes spatial and temporal redundancy of video data, resulting in a reduction in transmission time and communication bandwidth across a network and efficient storage. H.264, a widely adopted video compression standard, is the result of collaborative efforts between the ISO (International Organization for Standardization) Moving Picture Experts Group (MPEG) and the ITU (International Telecommunication Union) Video Coding Experts Group (VCEG). H.264 uses an array of algorithms for coding digital video to achieve better compression efficiency compared to previous standards. However, this efficiency increase comes at the cost of higher computational complexity for H.264 encoders. This thesis design and implement an H.264-compatible intra-frame video encoder on FPGA. The encoding algorithms, like intra prediction, transform, quantization, and entropy coding, are initially implemented and tested in MATLAB. Later, these algorithms are translated into VHDL language and evaluated through timing simulations vi in Vivado. The FPGA implementation is then tested using various input pixel sizes and video resolutions across multiple FPGA devices. The encoder supports all video resolutions and frame rates. | |
| dc.identifier.uri | https://hdl.handle.net/10323/18248 | |
| dc.relation.department | Electrical and Computer Engineering | |
| dc.title | A High-Speed, Light Weight Hardware Architecture for H.264- Compatible Compression on an FPGA |
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